Microarchitecture Optimization for Embedded Systems

Embedded applications are held to a higher standard than desktop applications along a number of dimensions. Not only must the functionality of the application be correct, it often must meet strict time constraints and function with restrictive resource limitations (e.g., memory size, power, weight). Conversely, the hardware systems used to execute embedded applications are often dedicated to that particular application, alleviating the need to be as general purpose as desktop systems. As a result, there is significant ongoing interest in the ability to build custom hardware platforms for which the design of the hardware is closely matched to the needs of the application. In addition, many applications can be characterized into distinct “phases” during which the application characteristics are often significantly different. A hardware platform that can closely match the needs of the application, even as the application characteristics change, is the goal of our research group. We are investigating the concept of a liquid architecture, in which the physical microarchitecture of a processor has the ability to be altered to adapt to the needs of a particular application, even so far as to be altered during application execution when the needs of the application change [1]. This can be realized in a number of ways: (1) via a soft-core processor deployed on an FPGA [2], and (2) via a configurable processor that is extensible at execution time [3,4]. Candidate architectural alternatives include ISA extensions (e.g., new instructions for frequent operations), cache system alterations (e.g., size, line length, associativity, write-back vs. write-through, specialized cache structures), co-processors, etc. While many architectural alternatives have been proposed in the past, and ideas for new architectural features can readily be proposed both today and into the future, the challenge we currently face is the need to quantitatively evaluate these alternatives with sufficient depth of understanding to decide whether a particular application (or phase of an application) is well matched to a particular candidate architecture. In short, given the ability to be flexible in the architectural choice at runtime, what architecture should be chosen for a given application? Answering the above question requires a quantitative assessment of the application’s performance as well as the resources consumed by the architecture (e.g., area, power). While traditionally answered via discrete-event simulation techniques, simulation is both time-consuming and has severe fidelity/completeness tradeoffs associated with it. For example, it is rare for a cycleaccurate simulation of a processor to model the activity of the operating system as well as the target application. We have built a system that enables the quantitative architectural assessments required to match architecture and application in a reasonable timeframe. In addition, the performance measurements do not impact the actual performance of the system under observation, as is the case with classical software-based performance monitoring techniques. The liquid architecture system we have constructed is based upon the LEON soft-core processor [2]. The LEON is a SPARC-compatible, synthesizable processor that has a reasonable level of configurability built into the original distribution. For example, the cache size, * This material is based upon work supported by the NSF under grant ITR–0313203.